The method and system are generally related to the verification of analog and mixed signal integrated circuits and more specifically to a system and method to translate verification subroutine commands.
Electronic design automation (EDA) is software for designing electronic blocks. There are several broad types of electronic signals, components and blocks: digital, analog and a mixture of digital and analog termed mixed signal. The electronic design generally comprises at least one of the following levels of circuit information: a system level, an architectural level, a dataflow level, an electrical level, a device level and a technology level and the like.
Digital signals have discrete input and output values “0” and “1”, occurring at discrete time values, typically tied to a clock signal. Digital components which input and output the digital signals typically have static pin outs and interaction protocols. Digital blocks comprised of the digital components have well established and well documented physical layouts and electrical interactions. Simulators for digital blocks are discrete time event driven simulators.
Analog signals generally have continuous input and output values that may vary over time. Analog components typically have customizable layouts in order to modify inputs, outputs, triggers, biases, etc. Therefore, due to customization, analog blocks comprised of the analog components may not have as well established or well documented physical layouts or electrical interactions as digital circuits. Simulators for analog blocks generally necessitate continuous time domain simulators.
Mixed signal blocks are a combination of digital signal blocks and analog signal blocks within a component being simulated. The most common options available for simulation are to simulate the component as a grouping of analog blocks, or to separately analyze the analog components/blocks and the digital components/blocks and translate the inputs and outputs at the boundaries of the digital and analog domains for inter-domain communication.
Within EDA there are two broad categories of circuit review that are related: simulation and verification. Simulation is a numerical solution set that predicts the behavior of a circuit. Verification is the systematic pursuit of describing the behavior of a circuit under relevant conditions (functional verification) and over manufacturing process variation (parametric verification). Therefore, verification generally necessitates a much more extensive review of the circuit, its operating conditions, and manufacturing operation variations than a simulation. It is possible to run a large number of simulations without verifying to any significant degree the functionality of a circuit. Verification is the mathematical modeling of circuit behavior and evaluation of circuit performance over a range of conditions. Ultimately, the measure of success of verification is to report how well the circuit design complies with the circuit specification. Analog and mixed signal verification methodology is struggling to keep pace with the complexity, cost, and computational demands of ever-growing analog and mixed signal circuits.
The number and complexity of verification test cases grows with the complexity of analog and mixed signal designs. Additionally, simulation speed decreases and memory utilization increases as the size of the circuit grows. Thus, the computational processing-power to verify a circuit may dramatically increase with circuit complexity. To make this issue more painful, verification normally occurs at the end of the design cycle where schedule delays are perceived to be most severe. Thus, verification is an activity that generally necessitates a significant amount of simulation processing-power for a small part of the overall design cycle, and therefore an efficient use of verification resources is generally necessitated to meet time to market demands.
Today's complex verification solutions specifically focus engineering on the verification activity to ensure that the operation of the circuit is fully and efficiently verified under pertinent conditions. This focused analog and mixed signal verification is much more manual and experience driven than digital verification. This sporadic interactive analog verification leaves companies at risk. The present disclosure may allow verification tasks to be defined at a higher level of abstraction. The present disclosure may allow efficient capture of complex relationships between stimulus or stimulus assertions and output measurements or output assertions. The present disclosure may allow the test of transistor level circuits, circuits implemented with behavioral models, or circuits that contain a combination of behavioral models and transistor level implementations. Standard branch contribution statements cannot be used in conditional, looping, nomenclature or analysis based statements, unless the conditional expression is a constant expression. For purposes of differentiation, we are calling these standard branch contribution statements as direct branch contribution statements. In this disclosure an indirect branch contribution statement (IBCS) is more powerful than a direct branch contribution statement (DBCS). Specifically, indirect branch contribution statements can be used in conditional and looping constructs that are dynamic with respect to the user's design, design configuration, simulation/analysis configuration, verification state, and verification history. There is a long felt need for independent branch contribution statements to be used in conditional, looping, nomenclature or analysis based statements or to return different arguments resulting from ongoing analysis.
In addition, the increasing complexity of the designs requires more traceability back to the product specification. Today many customers and industry require documentation of specific verification tests that validate each specification and test condition. The present disclosure includes the concept of high-level indirect branch contribution statements that can include parameters that link back to a specification database. These parameters can include but are not limited to specification limits, test stimulus conditions (for example, a supply voltage), and measurement requirements (for example, a net crossing a certain value). In this disclosure, at the time of the translation of the verification commands, the specification database can be accessed and the parameters replaced with the exact corresponding values from the specification database. The other option is to leave the linked parameters in the netlist and access the specification database to extract the parameter values at the time of simulation.
Robust verification of analog and mixed signal circuits generally necessitates a significant investment in test benches, performance analysis routines, and macro-models that may be used to accelerate the simulations. The complexity of this collateral grows with the complexity of the analog and mixed signal integrated circuits to be verified. As a design team adds design resources it also needs to add verification resources, adding to the cost of the design. The efficient use of those resources becomes paramount due to the inevitable time constraints that are imposed at the end of the design cycle, when companies are trying to get a product to market.
The current technology trajectory, within the electronics manufacturing industry, is to move more and more toward single chip designs, called Systems on a Chip (SoC), or multi-chip modules (MCM) where multiple chips are included in one package. Most systems on a chip and multi-chip modules generally necessitate some level of mixed signal verification. As mixed signal designs continue to increase in size and complexity, this places additional burdens on verification to insure first pass design success and reduce the time-to-market. Although the complexity of analog and mixed signal ASIC design has followed Moore's law, innovations in design verification generally have not.
Valuable design time and computational resources as well as expensive simulator resources may be specifically focused by the disclosed method for translating verification subroutine commands. The method makes the capture of complex stimulus as well as capture of output assertions and measurements more efficient. The resulting intelligent test benches identify areas that fail verification and, by greatly reducing the need for manual interpretation of results, provide much more immediate feedback to the design team and design management. Improving the test efficiency (i.e., not wasting simulation time and reducing time for output analysis) allows more efficient use of resources. In addition by connecting critical parameters to a specification database, the translated commands can access the latest version of the specification and provide traceability from the specification to the resulting verification test and outcome.
This disclosure is related to translating verification subroutine commands during verification of an electronic design for analog and mixed signal (A/MS) application specific integrated circuits (ASICs) and linking critical parameters back to a specification database. Analog and mixed signal integrated circuits exist in many modern electronic devices, and these circuits needs to be verified through simulation prior to fabrication.